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Design & Test of Computers
CALL FOR PAPERS
Presilicon simulation, verification, and emulation cannot guarantee fault-free silicon products: Both design errors and manufacturing defects do happen. Industry surveys show that up to 75% of all IC designs require one or more design respins. Yield ramping is extremely important, especially for advanced process technology nodes. We need to learn from early, prototype silicon in order to improve the design process, the manufacturing process, or both. The good news when studying silicon is that we are looking at the “real thing”; it is inherently more accurate and faster than any simulation model used in the presilicon phase. However, the bad news is that controllability and observability are difficult, and they get more difficult with every process technology node, requiring special design measures up front.
IEEE Design & Test seeks original manuscripts for a special issue on silicon debugging and diagnosis, scheduled for publication in May-June 2008. The objective of this special issue is to share insights on technical challenges and industrial applications in this area, as well as advanced methodologies and solutions in design, test, and diagnosis. Topics of interest include (but are not limited to):
|Submission and Review Procedures|
Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at https://mc.manuscriptcentral.com/cs-ieee. Indicate that you are submitting your article to the special issue on “Silicon Debugging and Diagnosis.” All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 150 words) and including a maximum of 12 References (50 for surveys). This amounts to about 4,200 words of text and five figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, passive to active voice, logical organization, readability, and adherence to style. Please see IEEE D&T Author Resources at http://www.computer.org/dt/author.htm, then scroll down and click on Author Center for submission guidelines and requirements.
More information at http://www.computer.org/portal/pages/design/content/0508cfp.html. Please direct questions regarding this special issue to Guest Editors.
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