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IEEE International High-Level Design, Validation and Test Workshop
(HLDVT'07)

Nov. 7-9, 2007
Irvine, CA, USA

http://www.hldvt.com/07

CALL FOR PAPERS
Workshop Scope -- Submissions -- Committees
Workshop Scope

HLDVT 2007 is the twelfth in a series of annual workshops designed to bring together a community of researchers in the areas of design, validation, and test.

The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum in recent years for researchers and practitioners to discuss the practical issues associated with simulation and validation of extremely large designs. This year, the theme is Challenges in multi-core design, validation and test.

Topics of interest include:

  • Simulation-Based Validation
  • Formal Verification
  • Design Abstraction & Behavioral Modeling
  • Error Trace Interpretation & Debugging
  • Hybrid SAT/BDD/ATPG Methods
  • On-Chip and Core-Based Testing
  • Test Generation for Defects, Design Errors, and Delay
  • Design/Synthesis for Test
  • Hardware/Software Co-Validation
  • Emulation and Prototyping
  • Design from Abstract Specifications

Submissions

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The Program Committee invites authors to submit papers not to exceed 8 pages (10pt minimum font size, reasonable margins and line spacing) describing original and unpublished work. On the title page, please indicate: paper title, name and affiliations of all authors, and the topic category. Also identify a contact author and provide complete mailing address, phone number, fax number and an e-mail address. Panel proposals are also invited. All submissions must be made electronically in PDF or Postscript format using the paper submission webpage: http://www.hldvt.com/submissions.

Please ensure that your PDF or Postscript file is readable by Acrobat Reader or Ghostview. The submission of an paper or panel proposal will be considered evidence that upon acceptance, the author(s) will present their paper or organize their panel at the workshop.

Submission deadline: June 16, 2007
Final manuscript: September 13, 2007

Authors of selected HLDVT'07 papers will be invited to submit extended versions for a special issue of a selected IEEE publication, to be published in 2008.

Additional information are available at http://www.hldvt.com/07. Questions regarding paper submissions and the program may be addressed to the program chair: Yatin Hoskote, programchair@hldvt.com. Other questions may be addressed to the general chair: Michael Hsiao, generalchair@hldvt.com.

Committees
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General Chair
Michael Hsiao, Virginia Tech

Program Chair
Yatin Hoskote, Intel

Past Chair
Robert Jones, Intel

Finance Chair
Priyank Kalla, Univ. of Utah

Publicity Chair
Ismet Bayraktaroglu, Sun

Local Arrangements Chair
Vijay Nagasamy, NEC Electronics

Program Committee
Mark Aagaard, Univ. of Waterloo
Samar Abdi, UC Irvine
Jacob Abraham, Univ. of Texas
Hussain Al-Asaad, UC Davis
Felice Balarin, Cadence Berkeley Labs
Valeria Bertacco, Univ. of Michigan
Tim Cheng, UC Santa Barbara
Scott Davidson, Sun
Farzan Fallah, Fujitsu Labs of America
Franco Fummi, Univ. di Verona
Kiyoharu Hamaguchi, Osaka Univ.
Ian Harris, UC Irvine
John Hayes, Univ. of Michigan
Harry Hsieh, UC Riverside
Alan Hu, Univ. British Columbia
Michael Kishinevsky, Intel
Ed McCluskey, Stanford Univ.
Alex Orailoglu, UC San Diego
Wolfgang Rosenstiel, Tubingen Univ.
Pablo Sanchez, Univ. of Cantabria
Sandeep Shukla, Virginia Tech
Lionel Torres, Univ. of Montpellier
Li-C.Wang, UC Santa Barbara
Jin Yang, Intel
Avi Ziv, IBM

Steering Committee
Bernard Courtois, CMP-TIMA
Sujit Dey, UC San Diego
Masahiro Fujita, Univ. of Tokyo
Prab Varma, Blue Pearl Software

For more information, visit us on the web at: http://www.hldvt.com/07

The IEEE International High-Level Design, Validation and Test Workshop (HLDVT'07 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee. HLDVT 2007 receives corporate support from IBM.


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TTTC 2ND VICE CHAIR
Joan FIGUERAS
Universitat Politècnica de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

FINANCE
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

DESIGN & TEST MAGAZINE
Tim CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG

Lucent Technologies
- USA
Tel. +1-732-949-5539
E-mail chenhuan@lucent.com

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Institute of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal University of Rio Grande do Sul - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

INTERNATIONAL TEST CONFERENCE
Jill E. SIBERT
Raspberry Comm.
- USA
Tel. +1-484-894-1111
E-mail jill_sibert@raspberrycom.com

TEST WEEK COORDINATION
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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