Verification and Test

Technical Activity Committee on VERIFICATION AND TEST

TAC Co-Chair:  Magdy S. ABADIR, m.abadir@freescale.com

Sujit Dey, dey@ece.ucsd.edu

As designs get larger every year, the two major problems faced by the semiconductor industry are to ensure that there are no bugs in the design and that the manufactured chips are defect-free. Given the rate of advance of the size, complexity and performance capabilities of integrated circuits, new directions need to be explored to solve problems in verification and test.

Although research in test and verification is exploring new directions which can deal with the complexities of emerging designs, the research communities in these areas have interacted very little. New techniques developed for verification are not applied to test, and sometimes long understood test strategies are not considered for formal verification. The goal of this TAC is to bring together the verification and test communities.

Simulation is the primary means used to validate the correctness of a design today. This should be the first area where the issues in verification and test are considered at the same time. Ultimately, formal verification techniques should be examined by the test community. (Test generation algorithms are beginning to be used to support formal verification).

We hope that this interaction will spur the development of tools for test generation and for formal verification that employ methods that are common to both domains.

One area of activity which will benefit both communities is the development of complex, public-domain benchmark designs. These will serve as a vehicle to spur the development of new techniques which can deal effectively with complexity, and will also serve to compare different techniques for solving various problems in the test and verification areas.