On-line Test

Technical Activity Committee on ON-LINE TESTING

TAC Chair:  Michael NICOLAIDIS, michael.nicolaidis@imag.fr
Subcommittee on Fault-Tolerant and Self-Calibrating Methodologies and EDA for Mitigating Reliability, Yield and Power Issues in Nano-CMOS

The increased complexity of electronic systems has seen increasing reliability needs in various application domains as well as pressure for low cost products. There is a corresponding increased demand for cost-effective on-line test techniques. These needs will increase dramatically in the near future, since very deep submicron and nano-technologies will impact adversely noise margins and make mandatory on-line testing solutions.

On-line testing and hardware fault tolerance are among the oldest fields of computer science. They was developed for improving reliability and/or availability of electronic systems. There are three main situations where reliability improvements are mandatory:

  • when the reliability of components produced by a fabrication process is very low,
  • when an application requires very high levels of reliability,
  • when a hostile environment reduces the reliability of components which, in normal conditions, provide acceptable reliability levels.

In the early age of computers, unreliable components made hardware fault tolerance mandatory. In the VLSI era, component reliability is improved dramatically, restricting the use of on-line testing techniques in specific application domains requiring very high levels of dependability (fault-tolerant computers, safety critical applications, etc.), and eventually evolving in hostile environments (e.g., space). Such applications often correspond to low volume production. In addition, the low number of these applications did not make attractive for CAD vendors the development of tools specific to the design of on-line testable ICS. The lack of such tools increases dramatically the effort for designing on-line testable ICs. Further, the low-volume production of such applications often does not justify such a high development cost, since it will impact dramatically the per product unit cost. As a matter of fact, techniques using off-the-shelf components, such as duplication or triplication are more often adopted, since they represent a much lower development cost although the production cost is relatively high.

We can expect this situation to be changing. Due to increasing reliability or availability requirements, various industrial sectors have increasing needs for on-line testing features. Such sectors are, for instance, railway control, satellites, avionics, telecommunications, control of critical automotive functions, medical electronics, industrial control, etc. Some of these applications concern mass production and should support the standardization of such techniques and the development of commercial CAD tools supporting them. Since silicon is “cheap”, such tools should make popular the design of on-line testable circuits. In addition to these trends, the high complexity of nowadays systems, require more efficient solutions. In fact, complex multi-chip systems of yesterday are today single-chip components. As a matter of fact, fault tolerant and fail-safe system designs of yesterday have to be integrated on chip, appealing for on-line testing techniques for VLSI.

While applications with increased reliability needs should support an increased use of on-line testing, another emerging factor will influence these trends drastically. In the past, progress in VLSI processes improved dramatically the reliability of electronic components, restricting the use of on-line testing in specific application domains. We are now in a point where these trends are reversed. Drastic device shrinking, low power supply levels and increasing operating speeds that accompany the technological evolution to deeper submicron, reduce significantly the noise margins and increase dramatically the soft error rates. As a consequence, technological progress will be blocked quickly if no particular actions are undertaken to cope with increasingly high soft-error rates (see M. Nicolaidis, “Design for Soft-Error Robustness to Rescue Deep Submicron Scaling,” 1998 ITC).

In this context, design for on-line testability seems to be the most adequate solution for designing soft-error robust circuits and pushing aggressively the limits of technological scaling.

In the view of these trends, the On-Line Testing TAC was created on April 1994 to further support these developments. Under the committee several actions were undertaken to stimulate the activities in the on-line testing domain, including the establishment of on-line testing as one of the basic topics in various conferences such as ITC, and VTS, the organization of several panel sessions and tutorials at ITC and VTS, the organization of journal special issues, including the February/April 1998 double issue of JETTA and the October/December 1998 issue of IEEE D&T of Computers. These activities should be intensified in the future as we start to understand that the nowadays VLSI design paradigm can not maintain acceptable levels of reliability for the future IC generations.

In the same perspective, the committee created the IEEE International On-line Testing Workshop, to establish an international forum for the domain. The topics of the workshop include (but are not limited to) the following ones:

  • Soft-error issues for very deep submicron
  • Radiation hardened/tolerant processes and design techniques
  • Concurrent checking
  • Periodic testing in the field
  • Sensors/detectors for on-line monitoring of current, temperature and other reliability relevant parameters
  • Field Diagnosis
  • Self-Checking digital, analog and mixed-signal circuits
  • Fault-tolerant and fail-safe systems
  • Coding theory
  • On-line testing in automotive, railway, avionics, industrial control and space applications
  • On-line and Off-line BIST
  • Synthesis of on-line testable circuits

For further information about the workshop please visit the Web Site: HTTP://tima-cmp.imag.fr/tima/ris/ioltw.html

A comprehensive presentation of on-line testing techniques can be found in:

M. Nicolaidis, Y. Zorian, “On-Line Testing for VLSI – A Compendium of Approaches,” Journal of Electronic Testing, Theory and Applications (JETTA), Volume 2, Nos. 1/2, February/April 1998, pp. 7-20.