MCM Testing

Technical Activity Committee on SiP and 3D IC Testing

TAC Chair:  Yervant ZORIAN, y.zorian@computer.org

All aspects of SiP and 3D IC testing including but not limited to:

  • wafer level, die level and stack level testing; known-good die technology;
  • Through Silicon Via fault models and tests;
  • temporary pressure- based and fixed contact-based carrier test;
  • known-good die testability approaches;
  • mechanical and contactless substrate testing;
  • SiP and 3D IC yield models;
  • ATE for SiP testing;
  • assembled module level test, testability, diagnosis and repair;
  • SiP and 3D IC level BIST;
  • testing printed circuit boards with SiPs and/or 3D ICs.

Upcoming conferences and symposia

IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) 2024

Submission of title, abstract, and author list: 23 February, 2024
Final Paper Submission: 29 February, 2024
Author Notification: 09 April, 2024
Conference Dates: July 3 – 5, 2024

IEEE European Test Symposium (ETS) 2024
Paper registration: December 8, 2023
Paper PDF upload: December 16, 2023
Notification: February 16, 2024
Conference: May 20-24, 2024

IEEE VLSI Test Symposium (VTS) 2024
Paper registration: October 9, 2023
Paper PDF upload: October 15, 2023
Questions to authors: December 9, 2023
Submission of rebuttal: December 14, 2023
Notification: December 23, 2023
Camera-ready upload: February 03, 2024
Conference: April 22-24, 2024