FPGA Test

Technical Activity Committee on FPGA TESTING

TAC Chair:  Michel RENOVELL, renovell@lirmm.fr

This FPGA Testing TAC has been recently formed in November 1999 with the aim of stimulating research and discussions around the new topic of FPGA testing.

Programmable logic in the form of field-programmable gate arrays has become now a widely accepted design approach for low- and medium-volume computing applications.

Low development costs and inherent functional flexibility have spurred the spectacular growth of this technology.

Only recently researchers have addressed the problem of testing this kind of circuits. The goal of the TAC is to provide an informal forum, bringing together designers and test researchers to address the problem of FPGA testing.