Activities

Purpose

The Technical Activities Group of TTTC is actively involved in: identifying key topic areas in test technology; initiating corresponding Technical Activity Committees (TACs) to coordinate interactions between experts of each topic area; and monitoring the outcome of these technical activities. These technical exchange forums, which include representation from both industry and academia, help identify the common issues of a given topic area and often have an impact on directions and concentration of effort in research. Currently, TTTC has many active TACs: IDDQ Testing, Manufacturing Test, MCM Testing, Memory Test, Mixed-Signal Testing, On-Line Testing, Software Testing, System Test, Test Economics and Test Synthesis.

TTTC TACs are encouraged to:

  • initiate appropriate meetings including Workshops and Tutorials
  • formulate special sessions or panel sessions for TTTC conferences/symposia
  • contribute technical material for publications, and organize special issues or sections
  • set up and run Round Tables for IEEE Design & Test of Computers
  • develop glossaries of terms (common terminology)
  • develop and maintain reference lists of key publications and/or products
  • conduct surveys regarding the current status and future needs in their area
  • provide a technical focal point for those interested in a topic area
  • expand the community of interested individuals and seek international representation from industry and academia prepare a membership data base (mailing lists) establish electronic mail reflectors for discussions among your members
  • prepare reviewers’ list for publications and conferences/symposia
  • provide speakers for conferences/symposia and for the TTTC Speakers Bureau
  • identify and initiate standards activities in conjunction with Standards Activities Board
  • propose nominations for Computer Society and other awards
  • develop funding requirements in conjunction with the TTTC Finance Chair
  • provide up-to-date information to the test community via the TTTC Newsletter

Each TAC identifies its area of interest in a statement of scope. If you are interested in joining a TAC you may directly contact the corresponding TAC Chair.

In addition, TTTC encourages “Student Activities”. Click here to have more info.


Board and Subassembly Test

ChairBill EKLOW, beklow@cisco.com

Defect Tolerance

ChairVincenzo PIURI, piuri@elet.polimi.it
Vice Chair: Cecilia METRA, cmetra@deis.unibo.it
Vice Chair: Nohpill PARK, npark@a.cs.okstate.edu

Economics of Test

Co-Chairs: Magdy S. ABADIR, m.abadir@freescale.com and Anthony P. AMBLER,ambler@ece.utexas.edu

Scope: To promote the awareness of economic issues in design and test, from device through to board, system, and field test. All aspects that pertain to costs will be covered, including product liability.

Embedded Core Test

Chair: Yervant ZORIAN, y.zorian@computer.org

FPGA Testing

Chair: Michel RENOVELL, renovell@lirmm.fr

Freeware Libraries

Chair: Burnell WEST, west@ieee.org

Hardware Security and Trust

Chair: Jim PLUSQUELLIC, jimp@ece.unm.edu

Scope: All aspects of Hardware Security and Trust including but not limited to: Trojan Detection and Isolation, Side channel Attacks and Countermeasures, Fault-based Attacks and Countermeasures, Intellectual Property Protection and Metering, Tools and Methodologies for Secure Hardware Design, Hardware Architectures for Cryptography, Hardware Security Primitives: PUFs and TRNGs, Trusted Platform and System Level Hardware Security, Interaction of Secure Hardware and Software, Non-destructive Reverse Engineering, CAD Tool Security and Trust, Supply Chain Security, Test and Security

High Level Design & Test

IEEE 1149.1

Chair: Christopher J. CLARKCclark@intellitech.com

IDDQ Testing

Chair: Manoj SACHDEV, msachdev@ece.uwaterloo.ca

Scope: To support the development of IDDQ/ISSQ testing of CMOS VLSI device testing by the co-ordination of standards in areas such as instrumentation and fault metrics.

Infrastructure IP

Chair: Yervant ZORIAN, y.zorian@computer.org

Scope: To support the development of infrastructure Intellectual Property for the integration of producible core-based integrated circuits.

Memory Test

Chair: Yervant ZORIAN, y.zorian@computer.org

Scope: The primary scope of Memory TAC is testing and reliability of stand-alone and embedded memories. In addition, Memory TAC works together with other Technical Committees such as TC on VLSI within the Computer Society and other societies such as Solid State Circuits Society within the IEEE. The scope of this joint effort expands from fabrication technology, memory design, testing and reliability.

MEMs Testing

Co-Chairs: Ronald D. BLANTON, blanton@ece.cmu.edu and Bernard COURTOIS,Bernard.Courtois@imag.fr

Mixed Signal Test

Chair: Bozena KAMINSKA, bozena@pultronics.com

Scope: to promote mixed-signal test activities by encouraging people to participate in conference sessions on this topic, in workshop organization, in recruiting new companies, in standard development, and in publicizing new mixed-signal test techniques via magazines (e.g. D&T magazine) and journals (e.g. IEEE Trans. Circuits & Systems).

Nano-based Devices

Chair: Fabrizio Lombardi, lombardi@ece.neu.edu

Nanometer Testing

Chair: Jaume SEGURA, dfsjsf4@clust.uib.es

On-Line Test

Chair: Michael NICOLAIDIS, michael.nicolaidis@imag.fr

Scope: To enable the exploration of the advanced on-line testing techniques by the industry and academia through active collaborations, and stimulate advanced research investigations on directions sensitive to influence the design of next generation reliable electronic systems.

Power-Aware Testing

Chair: Patrick GIRARD, girard@lirmm.fr

RF Testing

Chair: Iboun Taimiya SYLLA, isylla@ti.com

Scope: The purpose of this Technical Activity Committee is to explore and support development of RF Test solutions.

Silicon Debug and Diagnosis

Chair: Mike RICCHETTI, mike_ricchetti@ieee.org

SiP and 3D IC Testing

Chair: Yervant ZORIAN, y.zorian@computer.org

Scope: All aspects of SiP and 3D IC testing including but not limited to: wafer level, die level and stack level testing; known-good die technology; Through Silicon Via fault models and tests; temporary pressure- based and fixed contact-based carrier test; known-good die testability approaches; mechanical and contactless substrate testing; SiP and 3D IC yield models; ATE for SiP testing; assembled module level test, testability, diagnosis and repair; SiP and 3D IC level BIST; testing printed circuit boards with SiPs and/or 3D ICs.

System Test

Chair: Ian HARRIS, harris@ics.uci.edu

Scope: The purpose of this Technical Activity Committee is to provide a focal point for ongoing research in the area of System Test. To this end, we perform the following tasks:

  1. Encourage research in System Test by sponsoring activities at conferences and workshops.
  2. Provide an archive of information on System Test research.

Test Education

Chair: Sule OZEV, sule@ee.duke.edu

Test Compression

Chair: Rohit KAPUR, rkapur@synopsys.com

Test Resource Partitioning

Chair: Yervant ZORIAN, y.zorian@computer.org

Test Synthesis

Chair: Scott DAVIDSON, scott.davidson@eng.sun.com

Scope: All aspects of test synthesis including but not limited to: defining high-level testability requirements, measuring testability at high-level, technology- independent test synthesis, synthesis of self-test circuitry, performance-driven test synthesis and links to layout, logic or behaviour-level optimisation, tools to support test synthesis (DfT rule checking, re-timing optimization, insertion of test structures, hierarchical ATPG and fault simulation, integration with design synthesis, etc.). Web Page for ITC99 Benchmarks

Thermal Test

Co-Chair: Bernard COURTOIS, Bernard.Courtois@imag.fr

Verification and Test

Co-Chair: Magdy S. ABADIR, m.abadir@freescale.com